The invention in general relates to the fabrication of dielectric and ferroelectric metal oxides in integrated circuits, and in particular, to the formation of nonvolatile integrated circuit memories containing ferroelectric layered superlattice materials.
Ferroelectric compounds possess favorable characteristics for use in nonvolatile integrated circuit memories. See U.S. Pat. No. 5,046,043 issued Sep. 3, 1991 to Miller et al. A ferroelectric device, such as a capacitor, is useful as a nonvolatile memory when it possesses desired electronic characteristics, such as high residual polarization, good coercive field, high fatigue resistance, and low leakage current. Layered superlattice material oxides have been studied for use in integrated circuits. U.S. Pat. No. 5,434,102 issued Jul. 18, 1995 to Watanabe et al., and U.S. Pat. No. 5,468,684 issued Nov. 21, 1995, to Yoshimori et al., describe processes for integrating these materials into practical integrated circuits.
A typical ferroelectric memory in an integrated circuit contains a semiconductor substrate and a metal-oxide semiconductor field-effect transistor (MOSFET) electrically connected to a ferroelectric device, usually a ferroelectric capacitor. Layered superlattice materials currently in use and development comprise metal oxides. In conventional fabrication methods, crystallization of the metal oxides to produce desired electronic properties requires heat treatments in oxygen-containing gas at elevated temperatures. The individual heating steps in the presence of oxygen are typically performed at a temperature in the range of from 700xc2x0 C. to 900xc2x0 C. for 60 minutes to three hours. As a result of the presence of reactive oxygen at elevated temperatures, numerous defects, such as dangling bonds, are generated in the crystal structure of the semiconductor silicon substrate, leading to deterioration in the electronic characteristics of the MOSFET. Good ferroelectric properties have been achieved in the prior art using process heating temperatures at about 700xc2x0 C. to crystallize layered superlattice material. See U.S. Pat. No. 5,508,226 issued Apr. 16, 1996, to Ito et al. Nevertheless, the total duration of annealing and other heating steps at 700xc2x0 C. to 900xc2x0 C. in methods disclosed in the prior art is typically in a range of about two to four hours or more, which may be economically unfeasible. More importantly, long exposure times of 30 minutes or more in oxygen, even at the somewhat reduced temperature ranges, typically results in oxygen damage to the semiconductor substrate and other elements of the CMOS circuit.
After completion of the integrated circuit, the presence of oxides may still cause problems because oxygen atoms from a thin film of metal oxide layered superlattice material tend to diffuse through the various materials contained in the integrated circuit and combine with atoms in the substrate and in semiconductor layers, forming undesired oxides. Undesired diffusion of oxygen is proportional to temperature and to the amount of time at elevated temperature. The resulting oxides interfere with the function of the integrated circuit; for example, they may act as dielectrics in the semiconducting regions, thereby forming virtual capacitors. Diffusion of atoms from the underlying substrate and other circuit layers into the ferroelectric metal oxide is also a problem; for example, silicon from a silicon substrate and from polycrystalline silicon contact layers is known to diffuse into layered superlattice material and degrade its ferroelectric properties. For relatively low-density applications, the ferroelectric memory capacitor was placed on the side of the underlying CMOS circuit, and this reduced somewhat the problem of undesirable diffusion of atoms between circuit elements. Nevertheless, as the market demand and the technological ability to manufacture high-density circuits increase, the distance between circuit elements decreases, and the problem of molecular and atomic diffusion between elements becomes more acute. To achieve high circuit density by reducing circuit area, the ferroelectric capacitor of a memory cell is placed virtually on top of the switch element, typically a field-effect transistor (hereinafter xe2x80x9cFETxe2x80x9d), and the switch and bottom electrode of the capacitor are electrically connected by a conductive plug. To inhibit undesired diffusion, a barrier layer is located under the ferroelectric oxide, between the capacitor""s bottom electrode and the underlying layers. The barrier layer not only must inhibit the diffusion of oxygen and other chemical species that may cause problems; it must also be electrically conductive, to enable electrical connection between the capacitor and the switch. The maximum processing temperature tolerable with current barrier technology and fabrication methods is in a range of about 650xc2x0 C. to 700xc2x0 C. At temperatures in this range or higher for more than even a few minutes, the highest-temperature barrier materials quickly begin to degrade and to lose their diffusion-barrier properties. On the other hand, methods of forming layered superlattice materials disclosed in the prior art include heating the layered superlattice material and the associated memory stack in oxygen using RTP and furnace annealing (or in oxygen for part of the time, and in nonreactive gas part of the time) at temperatures in a range of about 650xc2x0 C. to 800xc2x0 C., for a minimum total duration of 60 minutes, but usually for two hours or longer. This prolonged heating at elevated temperature was done to achieve good crystallization of deposited layered superlattice materials. Nevertheless, such prolonged heating at elevated temperature typically damages semiconductor substrate, conductive plugs, diffusion barriers and other elements of integrated circuits.
It is common in the art to use rapid thermal processing (xe2x80x9cRTPxe2x80x9d) before furnace annealing to improve ferroelectric or dielectric properties of deposited metal oxide thin films, in particular, of layered superlattice materials. Methods using RTP before oxygen annealing are described in U.S. Pat. No. 5,648,114 issued Jul. 15, 1997 to Paz de Araujo et al., and U.S. Pat. No. 5,825,057 issued Oct. 20, 1998 to Watanabe et al. The RTP disclosed in the prior art is typically conducted at a temperature of 700xc2x0 C. to 850xc2x0 C. for a hold time of about 30 seconds, followed by an oxygen furnace anneal at 700-800xc2x0 C. for 30 to 60 minutes, followed by a furnace post-anneal at 700-800xc2x0 C. for 30 to 60 minutes in oxygen after formation of a top electrode and milling of the capacitor. In a variation, U.S. Pat. No. 6,326,315 B1 issued Dec. 4, 2001 to Uchiyama et al. teaches a ferroelectric anneal step in oxygen using an RTP-technique at 650xc2x0 C. for 30 minutes, followed by a furnace post-anneal at 650xc2x0 C. for 30 minutes in oxygen after formation of a top electrode and milling of the capacitor. Another approach of the prior art for making memory capacitors containing layered superlattice material is to conduct relatively low-temperature heating in oxygen (e.g., 600xc2x0 C. or less) and higher-temperature heating in inert gas (e.g., in nitrogen at 800xc2x0 C.). See, for example, U.S. Pat. No. 5,962,069 issued Oct. 5, 1999 to Schindler et al. Thus, these methods typically involve processing at elevated temperatures of 650xc2x0 C. or higher for a minimum total duration in excess of 60 minutes.
Metal oxide materials, such as barium strontium titanate (xe2x80x9cBSTxe2x80x9d) and other ABO3-type perovskites, are important for making integrated circuit thin film capacitors having high dielectric constants. Such capacitors are useful in fabricating integrated circuit memories, such as DRAMs. See for example, Kuniaki Koyama et al., xe2x80x9cA Stacked Capacitor with (BaxSr1-x)TiO3 For 256M DRAMxe2x80x9d in IDEM (International Electron Devices Meeting) Technical Digest, December 1991, pp. 32.1.1-32.1.4, and U.S. Pat. No. 5,122,923, issued to Shogo Matsubara et al. PZT and PLZT compounds are ABO3-type perovskites having ferroelectric properties useful in ferroelectric memories. Fabrication of integrated circuits containing ABO3-type perovskites and other dielectric and ferroelectric metal oxides using processes at elevated temperatures as described above with reference to layered superlattice materials results in similar problems of undesired diffusion and structural damage, resulting in degradation of electronic properties.
The present invention helps solve some of the problems mentioned above by providing a method with a low thermal budget (xe2x80x9cLTBxe2x80x9d) for fabricating an integrated circuit memory and other devices containing metal oxide material. In particular, embodiments in accordance with the invention provide integrated circuit devices containing ferroelectric layered superlattice having good ferroelectric and circuit characteristics, such as high-polarizability, low fatigue, low-leakage current, and high breakdown voltage.
The term xe2x80x9cthermal budgetxe2x80x9d herein refers generally to the total amount of time that an integrated circuit substrate is heated at elevated temperatures. The term xe2x80x9celevated temperaturexe2x80x9d used in this specification regarding the fabrication of metal oxide material, in particular, layered superlattice materials, generally means temperatures above 500xc2x0 C., typically in a range of about 500xc2x0 C. to 900xc2x0 C. It is an object of embodiments in accordance with the invention to reduce the thermal budget during fabrication of an integrated circuit device, while maintaining good ferroelectric and electronic properties. In one aspect, a method having a low thermal budget in accordance with the invention generally minimizes the cumulative heating time that an integrated circuit substrate is heated above 550xc2x0 C.; especially, it minimizes the thermal budget of operations conducted above 700xc2x0 C. The terms xe2x80x9ccumulative heating timexe2x80x9d, xe2x80x9ctotal heating timexe2x80x9d and related terms in the specification designate the time during fabrication steps that an integrated circuit substrate is heated at a temperature of 500xc2x0 C. or greater after an initial precursor coating is deposited on the substrate. During fabrication of an integrated circuit memory containing a capacitor comprising metal oxide dielectric material, in particular, ferroelectric layered superlattice material, the cumulative heating time refers practically to the total duration of substrate heating above 500xc2x0 C. from the point of starting to deposit an initial precursor coating on the substrate to the point of forming metallization and wiring layers on the completed memory cell. In the prior art, when a substrate including a ferroelectric coating was heated by RTP and furnace at a temperature of 650xc2x0 C. for 30 minutes, before forming a top electrode, and thereafter heated again in a furnace at 700xc2x0 C. for 60 minutes after formation of a top electrode, then the cumulative heating time was 90 minutes. In contrast, representative exemplary cumulative heating times in methods in accordance with the invention are about two to three minutes or less.
The term xe2x80x9cthermal budgetxe2x80x9d is also used herein in reference to a product of: (elevated processing temperature) multiplied by (time at elevated processing temperature). It has been observed that damage to an integrated circuit resulting from heating at a given temperature decreases by reducing the duration of heating at that temperature. Further, it has been observed that damage to the integrated circuit further decreases by utilizing RTP heating. Damage from heating an integrated circuit also decreases by heating at an increased temperature for a shorter amount of time. For example, generally less thermal damage occurs by heating at 800xc2x0 C. for 5 seconds, than by heating at 700xc2x0 C. for 10 minutes. Therefore, in selecting operating conditions in methods in accordance with the invention, a reduced heating time at a higher temperature is preferable to a longer heating time at a lower temperature. Heating of an integrated circuit substrate to achieve good crystallization of layered superlattice materials (or other metal oxide) and to minimize thermal damage to the integrated circuit is influenced by a number of variables, including, but not limited to: heating temperature; total heating time at elevated temperature (e.g., 800xc2x0 C.); thin film thickness; presence of oxygen; and, relative location of diffusion barrier layers. For example, a thin film of layered superlattice material having a thickness less than 100 nanometers (nm) generally requires a lower thermal budget to achieve good electronic properties than a thicker film. In the field of reaction engineering, it is known that the reaction rate is generally proportional to temperature, that is, the reaction rate increases with temperature. Nevertheless, the proportional relationship of reaction rate to temperature is usually not linear. In the art, it is generally held that reaction rate approximately doubles when temperature increases 10xc2x0 C. Thus, by increasing the temperature of a chemical reaction process by 30xc2x0 C., for example, the time required for reaction is reduced to a fraction of the time required without temperature increase. Efforts in the prior art to reduce thermal damage to integrated circuit memory capacitors typically aimed to minimize the temperature levels at which a memory circuit was heated. In contrast, methods in accordance with the present invention are designed to minimize the thermal budget of a process, that is, the product of heating time and heating temperature. Because the relation between reaction temperature and reaction rate is not linear, the heating time and thereby the thermal budget of a process are reduced by a relatively large amount through a relatively small increase in heating temperature. As a result, certain embodiments in accordance with the invention conduct heating of an integrated circuit memory substrate at temperatures higher than reported in the prior art, but during a much-reduced heating time.
As used in this specification, the term xe2x80x9cthermal budget valuexe2x80x9d denotes the product of: (elevated processing temperature, expressed in xc2x0 C.) multiplied by (time at elevated processing temperature, in seconds). The chemical reaction rates associated with precursor decomposition, compound formation and crystallization processes increase nonlinearly with temperature. A direct comparison of thermal budget values at different temperatures preferably includes multiplying the higher temperature by an adjustment factor greater than 1.0 to compensate for the relative non-linear change in reaction rates corresponding to a change in temperature. For example, if the minimal thermal budget value suitable to yield good results for a given set of operating and product parameters at an elevated temperature of 600xc2x0 C. is 36,000xc2x0 C.-sec (i.e., 600xc2x0 C.xc3x9760 sec), then the minimal thermal budget value, without adjustment, suitable for achieving similarly good results at an elevated temperature of 750xc2x0 C. is typically considerably less than 36,000xc2x0 C.-sec (i.e., less than 750xc2x0 C.xc3x9748 sec) because the reaction rates are much faster at 750xc2x0 C. The examples below describe low-thermal-budget fabrication in accordance with the invention of capacitors containing a thin film of layered superlattice material. It is understood, however, that the low thermal budgets described in the examples were not necessarily minimal thermal budgets; that is, it is believed that results as good as achieved with the low thermal budgets of the examples could have been achieved with even lower thermal budgets.
A thin film of layered superlattice material or other metal oxide in accordance with the invention typically has a thickness in a range of from 25 nm to 120 nm. In one aspect, a thin film formed in accordance with the invention has a thickness not exceeding 90 nm. In another aspect, a thin film has a thickness not exceeding 50 nm. In still another aspect, a thin film has a thickness not exceeding 40 nm. In still another aspect, the thin film has a thickness not exceeding 30 nm.
Efforts in the prior art to reduce heating temperature or heating times commonly did not change the thickness of the ferroelectric thin film in a memory capacitor. Decreasing the thickness of the ferroelectric thin film, in accordance with the invention, contributes to reducing the minimal thermal budget of a process, that is, the minimal thermal budget value for achieving good electronic and circuit properties.
An important feature of a method in accordance with the invention is the rapid thermal processing (xe2x80x9cRTPxe2x80x9d) treatment of a chemical precursor coating on an integrated circuit substrate to form crystallized layered superlattice material or other metal oxide. In an RTP technique, the temperature of a thin film containing metal atoms is ramped up to a xe2x80x9chold temperaturexe2x80x9d at a ramping rate, and held at the hold temperature for a time period, the xe2x80x9cholding timexe2x80x9d. In one aspect, a liquid precursor is deposited on a substrate, dried to form a solid film, and then an RTP is conducted. In another aspect, a precursor coating is deposited on a substrate by MOCVD, and then an RTP is conducted. An RTP operation in accordance with the invention is generally conducted in a conventional rapid thermal processing apparatus. In accordance with the invention, an initial RTP treatment of a substrate is generally at least partially conducted in an oxygen-containing atmosphere to enhance formation of the metal oxide bonds in polycrystalline layered superlattice materials and in other ferroelectric or dielectric compounds. It is contemplated, however, that an oxygen-free unreactive atmosphere may be used for a significant part of the RTP holding time.
In accordance with the invention, the oxidation and crystallization of precursor compounds to form layered superlattice material, or other ferroelectric or dielectric metal oxide material, depends on numerous factors. These factors include: ramping rate, holding time, hold temperature, oxygen-content of the RTP atmosphere, composition of the liquid precursor and the desired metal oxide material, and thickness of a precursor coating and resulting thin film of layered superlattice material. Ferroelectric layered superlattice materials, like the metal oxides SrBi2Ta2O9 (SBT) and SrBi2(Ta1-xNbx)2O9 (SBTN), where 0xe2x89xa6xxe2x89xa61, are particularly useful in nonvolatile memory applications, such as in FeRAMs and nondestructible read-out ferroelectric FETs. Polycrystalline thin films of these layered superlattice materials, as well as other layered superlattice materials, may be fabricated in accordance with the invention. In accordance with the invention, RTP hold temperatures suitable for forming a layered superlattice material are in the range of about from 500xc2x0 C. to 900xc2x0 C., preferably from 550xc2x0 C. to 800xc2x0 C. For ferroelectric layered superlattice materials such as strontium bismuth tantalate, SrBi2Ta2O9, and strontium bismuth tantalate, SrBi2(Ta1-xNbx)2O9, 0xe2x89xa6xxe2x89xa61, conducting RTP treatments with a nominal ramping rate of 100xc2x0 C./second and a cumulative holding time in a range of about 2xc2xd minutes (150 seconds) or less at hold temperatures in a range of about from 550xc2x0 C. to 750xc2x0 C. results in high remanent polarization, high breakdown voltage, low leakage current and low fatigue. Embodiments in accordance with the invention having a low thermal budget are also useful for providing a thin film of a metal oxide that is not a layered superlattice material, for example, an ABO3-type perovskite, such as barium strontium titanate.
In one aspect of the invention, it is not necessary to conduct any oxygen furnace anneals. Thus, in preferred embodiments in accordance with the invention, RTP treatment is the only heating technique performed at an elevated temperature above about 500xc2x0 C. to promote reaction and crystallization in the deposited thin film to form the desired polycrystalline layered superlattice material or other metal oxide. Because heating of a ferroelectric or a dielectric metal oxide thin film by RTP is very effective compared with other heating techniques, such as furnace annealing, the thermal budget of a method in accordance with the invention is minimized.
After the RTP has been conducted, the substrate containing the layered superlattice material thin film may optionally be given an oxygen furnace anneal. It is generally believed in the art that an oxygen furnace anneal conducted after an RTP tends to increase the remanent polarization of the layered superlattice material. Nevertheless, in one aspect of the invention, good electric properties and good physical properties of layered superlattice materials are achieved without a furnace anneal in either oxygen or in a nonreactive gas.
In embodiments of the invention in which a liquid precursor is deposited as a liquid coating on a substrate, the RTP is typically preceded by a step of baking the coating on the substrate at a temperature not exceeding 400xc2x0 C., typically in an oxygen-containing ambient, typically in O2 gas.
In one aspect, a method of fabricating a thin film of layered superlattice material comprises applying a precursor to a substrate to form a coating, and heating the substrate including the coating using rapid thermal processing at a temperature in a range of about from 500xc2x0 C. to 900xc2x0 C. for a cumulative heating time not exceeding 30 minutes, the precursor containing metal in effective amounts for forming a layered superlattice material upon heating the precursor. In still another aspect, the cumulative heating time does not exceed 5 minutes.
In one aspect, a low thermal budget method in accordance with the invention is particularly useful in the fabrication of an integrated circuit memory containing a thin film of layered superlattice material. In another aspect, heating the substrate comprises conducting a pre-TE RTP-treatment of the substrate including a coating, and further comprises a step of forming a top electrode layer on the coating after the pre-TE RTP-treatment, wherein heating the substrate further comprises conducting a post-TE RTP-treatment after forming the top electrode. In still another aspect, conducting a post-TE RTP-treatment is done in a nonreactive gas. In another aspect, a method in accordance with the invention further comprises a step of baking the coating on the substrate before heating the substrate. In another aspect, a pre-TE RTP treatment is conducted at a temperature in range of about from 500xc2x0 to 800xc2x0 C. for a pre-TE RTP heating time in a range of about from five seconds to 10 minutes. In another aspect, a post-TE RTP treatment is conducted at a temperature in range of about from 500xc2x0 to 800xc2x0 C. for a post-TE RTP heating time in a range of about from five seconds to 10 minutes.
In one aspect, a method in accordance with the invention comprises applying a first liquid coating on the substrate, baking the first coating to form a first dried coating, applying a second liquid coating on the first dried coating, and baking the second liquid coating to form the coating. In still another aspect, heating the substrate comprises conducting a pre-TE RTP-treatment of the substrate after baking the second liquid coating, and further comprises a step of forming a top electrode layer on the coating after the pre-TE RTP-treatment, wherein heating the substrate further comprises conducting a post-TE RTP-treatment after forming the top electrode. In still another aspect, a post-TE RTP-treatment is conducted in a nonreactive gas.
In one aspect, applying a precursor and heating the substrate comprises are applying a first liquid coating on the substrate, baking the first coating to form a first dried coating, conducting a first pre-TE RTP-treatment of the substrate after baking the first coating; applying a second liquid coating on the first coating after the first pre-TE RTP-treatment, baking the second liquid coating, and conducting a second pre-TE RTP-treatment of the substrate after baking the second liquid coating. In still another aspect, a method in accordance with the invention further comprises a step of forming a top electrode layer on the coating after the second pre-TE RTP-treatment, and heating the substrate comprises conducting a post-TE RTP-treatment after forming the top electrode layer. In still another aspect, the post-TE RTP-treatment is conducted in a nonreactive gas.
One aspect of the invention is formation of a thin film of layered superlattice material using MOCVD. In a related aspect, a metal organic precursor flows into a CVD reaction chamber to apply a precursor coating on a substrate.
In one aspect, the layered superlattice material comprises strontium bismuth tantalate. In another aspect, a precursor or a combination of precursors includes u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, and 0.7xe2x89xa6uxe2x89xa61.0, 2.0xe2x89xa6vxe2x89xa62.3, and 1.9xe2x89xa6wxe2x89xa62.1. In still another aspect, the layered superlattice material comprises strontium bismuth tantalum niobate. In another aspect, a precursor includes u mole-equivalents of strontium, v mole-equivalents of bismuth, w mole-equivalents of tantalum, and x equivalents of niobium, and 0.7xe2x89xa6uxe2x89xa61.0, 2.0xe2x89xa6vxe2x89xa62.3, 1.9xe2x89xa6wxe2x89xa62.1, 1.9xe2x89xa6xxe2x89xa62.1 and 1.9xe2x89xa6(w+x)xe2x89xa62.1.
In one aspect, a ferroelectric integrated circuit memory cell in accordance with the invention comprises a ferroelectric memory element including a polycrystalline ferroelectric thin film, and an electrode for applying an electric field to the ferroelectric thin film, the ferroelectric thin film having a thickness of 40 nm or less.
In one aspect of the invention, the substrate comprises a first electrode, and the method includes forming a thin film of layered superlattice material on the first electrode, then a second electrode on the thin film of layered superlattice material, after a pre-TE RTP, to form a memory capacitor, and subsequently performing a post-TE RTP operation. In a preferred embodiment, the first electrode and the second electrode contain platinum and titanium. The post-RTP is typically conducted at a temperature in the range of from 500xc2x0 C. to 900xc2x0 C., preferably 550xc2x0 C. to 800xc2x0 C., preferably for duration of 5 seconds to 5 minutes. In one aspect of the invention, the post-TE RTP-treatment is conducted in an oxygen-containing ambient, typically in O2 gas. In another aspect, post-TE RTP-treatment is conducted in a nonreactive ambient, typically in N2 gas. Preferably, an electrically conductive barrier layer is formed on the substrate prior to applying the precursor coating.
In one aspect, a method in accordance with the invention has a thermal budget value in a range of about from 2,500xc2x0 C.-sec to 960,000xc2x0 C.-sec, preferably less than 50,000xc2x0 C.-sec.
Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.